At the 2026 International Symposium on Circuits and Systems in Shanghai, Huawei introduced 'Tao's Law,' which replaces geometric scaling with time scaling for semiconductor advancement. The company claims to have already designed and mass-produced 381 chips under this principle and plans to launch a new Kirin phone chip using logic folding this autumn. This could represent a fundamental shift in semiconductor scaling beyond Moore's Law, potentially extending chip performance improvements without relying solely on shrinking transistor sizes. If validated, it may impact the entire industry's R&D direction and reduce dependence on extreme lithography. According to Huawei, Tao's Law achieves multi-level co-optimization from devices to systems by reducing time constants instead of geometric dimensions. The company projects that by 2031, high-end chips based on this law could reach transistor density equivalent to 1.4nm process technology.
Background
Moore's Law, which predicted transistor density doubling every two years, is approaching physical limits due to quantum effects and fabrication challenges. Traditional geometric scaling shrinks transistor dimensions to achieve denser chips. Time scaling instead focuses on reducing circuit delay times and improving architectural efficiency, potentially achieving better performance through temporal domain optimization. Logic folding is a technique that reuses hardware over multiple clock cycles to increase effective density.